Mentor: Dr. Ann Gordon-Ross
College of Engineering
"I applied to the Scholars program and got involved in research because I really wanted to bring my education beyond the class room. It is my goal to better practice the scientific method under the leadership of my mentor and peers while also deepening my knowledge in select fields of interest. I hope this program will be a good introduction to graduate research and pave the way for future studies. My end goal for this academic year is to acquire enough results to be able to author my first paper."
Electrical and Computer Engineering
- Digital Engineering
- Computer Design
Hobbies and Interests
Partial Bit-stream Compression and Compressibility Analysis
Field-programmable gate arrays (FPGAs) provide powerful and flexible solutions to digital design applications. They have excellent performance characteristics similar to an ASIC (application-specific integrated circuit) with the flexibility of a software program running on a typical microprocessor. FPGAs work by loading a software binary file to configure its hardware resources into the desired circuit at the hardware logic level. This binary input is called a bit-stream, and it is device specific based on the quantity and layout of hardware resources available inside the chip. Many of today’s FPGAs even offer the benefit of partial reconfiguration, meaning the FPGA is capable of reprogramming a select portion of the hardware while the rest remains unchanged. One of the obstacles that developers face when utilizing FPGAs is the time to physically load the bit-stream into the chip and the amount of memory the bit-stream occupies when stored. The idea of bit-stream compression has been thoroughly researched and many solutions to this problem exist today. The focus of my research is on how the bit-stream is created prior to compression with the goal that we may make the bit-stream more amiable to the compression scheme being utilized. More specifically, bit-streams begin with a netlist representative of the desired circuit created by the designers. This netlist gets passed into a placement and routing algorithm that optimizes the design for a specific FPGA based on input parameters such as area and performance. Placement is responsible for determining the optimal layout of the individual hardware blocks followed by routing which determines the best way to connect said blocks. The goal of my research is to determine if it is possible to alter the placement and routing algorithms such that they may be set to optimize the bit-stream for compressibility.